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HD64F2149YV Datasheet(PDF) 362 Page - Renesas Technology Corp

No. de pieza HD64F2149YV
Descripción Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
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HD64F2149YV Datasheet(HTML) 362 Page - Renesas Technology Corp

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Section 11 16-Bit Free-Running Timer
Rev. 3.00 Jan 18, 2006 page 334 of 1044
REJ09B0280-0300
11.3.6
Setting of Output Compare Flags A and B (OCFA, OCFB)
The output compare flags are set to 1 by an internal compare-match signal generated when the
FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last
state in which the two values match, just before FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 11.12 shows the timing of the setting of OCFA
and OCFB.
OCRA or OCRB
φ
Compare-match
signal
FRC
NN + 1
N
OCFA or OCFB
Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB)



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