M66596FP datasheet(49/131 Pages) RENESAS

49 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 49 of 127

3 Description of Operation

3.1 System control and oscillation control

This chapter describes the register operations that are necessary to the default settings of the controller, and the

registers necessary for power consumption control.

3.1.1

Resets

Table 3.1 shows a table of controller resets. For information on the initialized states of the registers following the

various reset operations, please refer to Chapter 2, Registers.

Table 3.1 Types of Resets

Name

Operation

H/W reset

”L” level input from the RST_N pin

S/W reset

Operation using the USBE bit of the SYSCFG

USB bus reset

Automatically detected by the controller from the

D+ and D- lines in tne Peripheral mode

3.1.2

Bus interface settings

Table 3.2 shows the bus interface settings for the controller.

Table 3.2 Bus interface settings

Bit name

Setting contents

PINCFG

LDRV

Control setting for the drive current

PINCFG

BIGEND

Byte Endian setting for the CPU being connected

This bit is effective in access to a FIFO register

DMAxCFG

DREQA

Active setting for the DREQx_N pin

DMAxCFG

DACKA

Active setting for the DACKx_N pin

DMAxCFG

DENDA

Active setting for the DENDx_N pin

DMAxCFG

OBUS

OBUS mode setting

INTENB1

INTL

Output sensing setting for the INT_N pin

3.1.3

Selection of the function

This controller can select either a Host function or a Peripheral function by software. To select USB function for

the controller, set the DCFM bit of the SYSCFG register. Changing the DCFM bit (writing access) should be done

with the internal clock stopped (“SCKE=0”).

3.1.4

Enabling Hi-Speed operation

With this controller, either Hi-Speed operation or Full-Speed operation can be selected as the USB communication

speed (communication bit rate), using software. To enable Hi-Speed operation for the controller, set the HSE bit of

the SYSCFG register to “1”. Changing the HSE bit should be done with the internal clock stopped (“SCKE=0”).

If Hi-Speed operation has been enabled, the controller executes the reset handshake protocol, and the USB

communication speed is set automatically. The results of the reset handshake can be confirmed using the RHST bit

of the DVSTCTR register.

If Hi-Speed operation has been disabled, the controller will use Full-Speed operation.

M66596FP Datasheet(PDF) 49 Page - Renesas Technology Corp

M66596FP Datasheet(HTML) 49 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL