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SPFD54126B
© ORISE Technology Co., Ltd.
Proprietary & Confidential
8
NOV. 20, 2006
Preliminary Version: 0.2
4.1.1. System Interface
The SPFD54126B supports three high-speed system interfaces:
1. 80-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports.
2. 68-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports.
3. 3-pin 9-bits Serial Peripheral Interface (SPI).
The SPFD54126B has a 16-bit index register (IR) and two 18-bit data registers, a write-data register (WDR) and a read-data register (RDR).
The IR register is used to store index information from control registers. The WDR register is used to temporarily store data to be written for
register control and internal GRAM. The RDR register is used to temporarily store data read from the GRAM. When graphic data is written
to the internal GRAM from MCU/graphic engine, the data is first written to the WDR and then automatically written to the internal GRAM in
internal operation. When graphic data read operation is executed, graphic data is read via the RDR from the internal GRAM. Therefore,
invalid data is first read out to the data bus when the SPFD54126B executes the 1
st read operation. Thus, valid data can be read out after
the SPFD54126B executes the 2
nd read operation.
4.1.2. External Display Interface
The SPFD54126B supports external RGB interface for picture movement display.
The SPFD54126B allows switching between one of the external display interfaces and the system interface via pin configuration so that the
optimum interface is selected for still / moving picture displayed on the screen.
When the RGB interface is chosen, display operations are synchronized with external supplied signals, VSYNC, HSYNC, and DOTCLK.
Moreover, valid display data (DB17-0) is written to GRAM, which synchronized with signal (DE) enabling.
4.1.3. Address Counter (AC)
SPFD54126B features an Address Counter (AC) giving an address to the internal GRAM. The address in the AC is automatically updated
plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM.
4.1.4. Graphics RAM (GRAM)
SPFD54126B features a 87120-byte (176 x 220x 18/8) Graphic RAM (GRAM).
4.1.5. Grayscale Voltage Generating Circuit
SPFD54126B has true 6-bit resolution D/A converter, which generates 64 Gamma-corrected values and cooperates with OP-AMP structure
to enhance display quality. The grayscale voltage can be adjusted by grayscale data set in the γ-correction register. For details, see the
“γ-Correction Function” section.
4.1.6. Timing Controller
SPFD54126B has a timing controller which can generate a timing signal for internal circuit operation such as gate output timing, RAM
accessing timing, etc.
4.1.7. Oscillator (OSC)
The SPFD54126B also features an internal oscillator to generate RC oscillation with an internal resistor. In standby mode, RC oscillation is
halted to reduce power consumption. See “Oscillator” for details.
4.1.8. Source Driver Circuit
SPFD54126B consists of a 528-output source driver circuit (S1 ~ S528). Data in the GRAM are latched when the 528
th bit data is input.
The latched data controls the source driver and generates a drive waveform.
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
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