BUF16821 datasheet(13/29 Pages) EPCOS

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Reading: DAC/VCOM/OTHER Register (Volatile

BUF16821

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The BUF16821 acknowledges each data byte. If the

single DAC register procedure.

master terminates communication early by sending a

5. Send a STOP or START condition on the bus.

STOP or START condition on the bus, the specified

The

BUF16821

acknowledges

each

byte.

terminate communication, send a STOP or START

condition on the bus. Only DAC registers that have

output voltage; see the Updating the DAC Outputs

received both bytes of data are updated.

section.

The process of updating multiple DAC/VCOM registers

begins the same as when updating a single register.

Memory)

However, instead of sending a STOP condition after

Reading a register returns the data stored in that

writing the addressed register, the master continues

DAC/VCOM/OTHER register.

to send data for the next register. The BUF16821

automatically

and

sequentially

steps

through

To read a single DAC/VCOM/OTHER register:

subsequent registers as additional data are sent. The

1. Send a START condition on the bus.

process continues until all desired registers have

2. Send the device address and read/write bit =

been updated or a STOP or START condition is sent.

LOW. The BUF16821 acknowledges this byte.

To write to multiple DAC/VCOM registers:

3. Send the DAC/VCOM/OTHER pointer address

1. Send a START condition on the bus.

byte. Set bit D7 = 0 and D6 = 0; bits D5–D0 are

2. Send the device address and read/write bit =

the

DAC/VCOM/OTHER address. NOTE: The

LOW. The BUF16821 acknowledges this byte.

BUF16821 stores and returns data only from

these addresses:

3. Send either the OUT1 pointer address byte to

start at the first DAC, or send the pointer address

–

000000 through 001111

byte for whichever DAC/VCOM is the first in the

–

010010

sequence of DACs/VCOMs to be updated. The

–

010011

BUF16821 begins with this DAC/VCOM and steps

–

111100 through 111111

through subsequent DACs/VCOMs in sequential

It returns 0000 for reads from 010000 and

order.

010001,

and

010100

through

010111.

See

4. Send the bytes of data; begin by sending the

Table 4 for valid DAC/VCOM/OTHER addresses.

most significant byte (bits D15–D8, of which only

4. Send a START or STOP/START condition.

bits D9 and D8 have meaning, and bits D15–D14

5. Send the correct device address and read/write

must not be 01), followed by the least significant

bit = HIGH. The BUF16821 acknowledges this

byte (bits D7–D0). The first two bytes are for the

byte.

DAC/VCOM addressed in the previous step. The

DAC/VCOM register is automatically updated after

6. Receive two bytes of data. They are for the

receiving the second byte. The next two bytes are

specified register. The most significant byte (bits

for the following DAC/VCOM. That DAC/VCOM

D15–D8) is received first; next is the least

significant byte (bits D7–D0). In the case of

This process continues until the registers of all

DAC/VCOM channels, bits D15–D10 have no

following DACs/VCOMs have been updated. The

meaning.

BUF16821 continues to accept data for a total of

7. Acknowledge after receiving the first byte.

18 DACs; however, the two data sets following

8. Send a STOP or START condition on the bus or

the 16th data set are meaningless. The 19th and

do not acknowledge the second byte to end the

20th data sets apply to VCOM1 and VCOM2. The

read transaction.

write disable bit cannot be accessed using this

method. It must be written to using the write to a

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