STTS424E02BDA3F datasheet(32/51 Pages) STMICROELECTRONICS

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SPD EEPROM operation

STTS424E02

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5.5.1

Byte write

After the Device Select Code and the address byte, the bus master sends one data byte. If

the addressed location is hardware write-protected, the device replies to the data byte with

NoAck, and the location is not modified. If, instead, the addressed location is not Write-

protected, the device replies with Ack. The bus master terminates the transfer by generating

a Stop condition, as shown in Figure 12.

5.5.2

Page write

The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided

that they are all located in the same page in the memory: that is, the most significant

memory address bits are the same. If more bytes are sent than will fit up to the end of the

page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to

become overwritten in an implementation dependent way.

The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the

device if Write Control (WC) is Low. After each byte is transferred, the internal byte address

counter (the 4 least significant address bits only) is incremented. The transfer is terminated

by the bus master generating a Stop condition.

Figure 12.

Write mode sequences in a non write-protected area of SPD

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01941

DATA IN N

ACK

R/W

ACK

R/W

ACK

STTS424E02BDA3F Datasheet(PDF) 32 Page - STMicroelectronics