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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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STLC1502 Datasheet(PDF) 39 Page - STMicroelectronics |
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STLC1502 Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 81 page  39/81 STLC1502 Figure 12: IRQ control block 7.4.3 Interrupt register map [0x0C100000] The base address of the timer register is 0x0C100000 The offset of any particular register from the base address is the following. Address Register Name R/W Notes Int.Base + 0x00 IRQStatus R For every IRQ interrupt cause, a ‘1’ means an active pending interrupt that has to be served by the ARM Int Base+ 0x04 IRQRawStatus R For every IRQ interrupt source, a ‘1’ means an active pending interrupt “before” the mask (w/ o considering the mask) Int.Base + 0x08 IRQEnableSet R/W For every IRQ interrupt source, a ‘0’ means that even if an interrupt source is active, it has to be stopped (masked). The write operation of 1 to a given bit, enable the corresponding interrupt INTERRUPT_MASK Enable nIRQ Other Interrupt Bit Slices IRQRawStatus IRQStatus Interrupt Source Interrupt Pending |
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