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AT89C51ID2-RDTIM Datasheet(PDF) 70 Page - ATMEL Corporation |
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AT89C51ID2-RDTIM Datasheet(HTML) 70 Page - ATMEL Corporation |
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70 / 159 page  70 AT89C51ID2 4289A–8051–09/03 Table 52. IPL1 Register IPL1 - Interrupt Priority Register (B2h) Reset Value = XXXX X000b Bit addressable Table 53. 7654 3210 ----- SPIL TWIL KBDL Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2SPIL SPI interrupt Priority bit Refer to SPIH for priority level. 1TWIL TWI interrupt Priority bit Refer to TWIH for priority level. 0KBDL Keyboard interrupt Priority bit Refer to KBDH for priority level. |
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