TAS2781RYYR datasheet(28/90 Pages) TI2

28 / 90 page

Figure 8-5. Current Limit vs Battery Voltage

The power limiter can be applied to either PVDDL (one cell battery) or PVDDH (multi-cell battery). By default it is

set on PVDDL and can be canged to PVDDH by using bit PWR_LIM_SRC.

8.4.10 Clocks

The device clocking is derived from the SBCLK input clock. The tables below show the valid SBCLK clock

frequencies for each sample rate and SBCLK to FSYNC ratio.

If the sample rate is properly configured via the SAMP_RATE[2:0] register bits, no additional configuration is

required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and

SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. After the clock

error is detected, the device will enter a low power halt mode after a time set by CLK_HALT_TIMER[2:0] register

bits if DIS_CLK_HALT bit is low. Additionally, the device can automatically power up and down on valid clock

signals if CLK_PWRUD register bit is set to high. The device sampling rate should not be changed while this

feature is enabled. In this mode the DIS_CLK_HALT bit register should be set low in order for this feature to

work properly.

Table 8-5. Supported SBCLK Frequencies [MHz] for 48 kHz Based Sample Rates

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

125

0.512

0.768

1.024

1.526

0.576

0.768

1.152

1.536

2.304

0.512

0.768

1.024

1.536

2.048

3.072

0.768

1.152

1.536

2.304

3.072

4.608

1.536

2.304

3.072

4.608

6.144

9.216

192

3.072

4.608

6.144

9.216

12.288

18.432

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

128

192

250

256

384

500

512

2.048

3.072

4.096

6.144

8.192

3.072

4.608

6.144

9.216

12.288

4.096

6.144

8.192

12.288

16384

6.144

9.216

12.288

18.432

24.576

12.288

18.432

24.576

192

24.576

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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