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CHR71000 Datasheet(PDF) 44 Page - ams-OSRAM AG |
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CHR71000 Datasheet(HTML) 44 Page - ams-OSRAM AG |
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44 / 54 page ![]() CHR71000 Register description Datasheet • PUBLIC • Document Feedback DS000427 • v2-01 • 2026-Mar-18 44 / 54 / Addr Bits Name Description Default Recommended 66 [7:4] reg_offset_1[11:8] MSB of DAC offset 8 8 67 [7:0] reg_offset_2[7:0] DAC offset of even pixels in channel 1 0 0 68 [7:0] reg_offset_3[7:0] DAC offset of odd pixels in channel 1 0 0 69 [3:0] reg_offset_2[11:8] MSB of DAC offset 8 8 69 [7:4] reg_offset_3[11:8] MSB of DAC offset 8 8 70 [7:0] reg_offset_4[7:0] DAC offset of even pixels in channel 2 0 0 71 [7:0] reg_offset_5[7:0] DAC offset of odd pixels in channel 2 0 0 72 [3:0] reg_offset_4[11:8] MSB of DAC offset 8 8 72 [7:4] reg_offset_5[11:8] MSB of DAC offset 8 8 73 [7:0] reg_offset_6[7:0] DAC offset of even pixels in channel 3 0 0 74 [7:0] reg_offset_7[7:0] DAC offset of odd pixels in channel 3 0 0 75 [3:0] reg_offset_6[11:8] MSB of DAC offset 8 8 75 [7:4] reg_offset_7[11:8] MSB of DAC offset 8 8 76 [7:0] reg_offset_8[7:0] DAC offset of even pixels in channel 4 0 0 77 [7:0] reg_offset_9[7:0] DAC offset of odd pixels in channel 4 0 0 78 [3:0] reg_offset_8[11:8] MSB of DAC offset 8 8 78 [7:4] reg_offset_9[11:8] MSB of DAC offset 8 8 79 [7:0] reg_offset_10[7:0] DAC offset of even pixels in channel 5 0 0 80 [7:0] reg_offset_11[7:0] DAC offset of odd pixels in channel 5 0 0 81 [3:0] reg_offset_10[11:8] MSB of DAC offset 8 8 81 [7:4] reg_offset_11[11:8] MSB of DAC offset 8 8 82 [7:0] reg_offset_12[7:0] DAC offset of even pixels in channel 6 0 0 83 [7:0] reg_offset_13[7:0] DAC offset of odd pixels in channel 6 0 0 84 [3:0] reg_offset_12[11:8] MSB of DAC offset 8 8 84 [7:4] reg_offset_13[11:8] MSB of DAC offset 8 8 85 [7:0] reg_offset_14[7:0] DAC offset of even pixels in channel 7 0 0 86 [7:0] reg_offset_15[7:0] DAC offset of odd pixels in channel 7 0 0 |
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