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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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PM6670 Datasheet(PDF) 37 Page - STMicroelectronics |
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PM6670 Datasheet(HTML) 37 Page - STMicroelectronics |
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37 / 53 page  PM6670 Device description 37/53 7.3 S3 and S5 power management pins According to DDR2/3 memories supply requirements, the PM6670 can manage all S0 to S5 system states by connecting S3-S5 pins to their respective sleep-mode signals in the notebook's motherboard. Keeping S3 and S5 high, the S0 (Full-On) state is decoded and the outputs are alive. In S3 state (S5 = 1, S3 = 0), the PM6670 maintains VDDQ and VTTREF outputs active and VTT output in high-impedance as needed. In S4/S5 states (S5 = S3 = 0) all outputs are turned off and, according to DSCG pin voltage, the proper Soft-End is performed. Table 11. S3 and S5 Sleep-states decoding S3 S5 System State VDDQ VTTREF VTT 1 1 S0 (Full-On) OnOnOn 0 1 S3 (Suspend-To-RAM) On On Off (Hi-Z) 0 0 S4/S5 (Suspend-To-Disk) Off (Discharge) Off (Discharge) Off (Discharge) |
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