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STM32F101X6 Datasheet(PDF) 51 Page - STMicroelectronics

No. de pieza STM32F101X6
Descripción Electrónicos  Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces
PDF  74 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101X6 Datasheet(HTML) 51 Page - STMicroelectronics

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STM32F101xx
Electrical characteristics
51/74
Figure 21.
I/O AC characteristics definition
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 33).
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
Figure 22.
Recommended NRST pin
protection
1.
The reset network protects the device against parasitic resets.
2.
The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 36. Otherwise the reset will not be taken into account by the device.
ai14131
10%
90%
50%
tr(IO)out
OUTPUT
EXT ERNAL
ON 50pF
Maximum fr equency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)
10%
50%
90%
when loaded by 50pF
T
tr(IO)out
Table 36.
NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST Input low level voltage
–0.5
0.8
V
VIH(NRST)
NRST Input high level voltage
2
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
200
RPU
Weak pull-up equivalent resistor(1)
1.
The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum
(~10% order)
.
VIN = VSS
30
40
50
k
Ω
VF(NRST)
NRST Input filtered pulse(2)
2.
Values guaranteed by design, not tested in production.
100
ns
VNF(NRST) NRST Input not filtered pulse
(2)
300
ns
ai14132b
STM32F10xxx
RPU
NRST(2)
VDD
FILTER
Internal Reset
0.1 µF
External
reset circuit(1)



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