PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 13 of 30
These generators are enabled by the associated BOE[x]
signals listed in Table 8 (when the BISTLE latch enable input
is HIGH). When enabled, a register in the associated transmit
channel becomes a signature pattern generator by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit
violation
symbols.
This
provides
a
predictable
yet
pseudo-random sequence that can be matched to identical
LFSR
in
the
attached
remote
Receiver(s),
the
CYP15G0401RB for example. To enable BIST for serial link
testing, ensure that the remote HOTLink receivers are using
the recovered clock from the associated receive CDR PLL to
clock the receive parallel interface (for example RXCKSEL =
MID for the CYP15G0401RB device).
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator in the associated transmit
channel. When BISTLE returns LOW, the values of all BOE[x]
signals are captured in the BIST Enable Latch. These values
remain in the BIST Enable Latch until BISTLE is returned
HIGH to open the latch. A device reset (TRSTZ sampled
LOW), presets the BIST Enable Latch to disable BIST on all
channels.
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel.
Serial Output Drivers
The serial interface Output Drivers use high-performance
differential
CML
(Current
Mode
Logic)
to
provide
source-matched drivers for the transmission lines. These
Serial Drivers accept data from the Transmit Shifters. These
outputs have signal swings equivalent to that of standard
PECL drivers, and are capable of driving AC-coupled optical
modules or transmission lines. To achieve OBSAI RP3
compliancy, the serial output drivers must be AC-coupled to
the transmission medium.
Each Serial Driver can be enabled or disabled separately
through the BOE[7:0] inputs, as controlled by the OELE
latch-enable signal. When OELE is HIGH, the signals present
on the BOE[7:0] inputs are passed through the Serial Output
Enable Latch to control the Serial Driver. The BOE[7:0] input
associated with a specific OUTxy
± driver is listed in Table 8.
When OELE is HIGH and BOE[x] is HIGH, the associated
Serial Driver is enabled. When OELE is HIGH and BOE[x] is
LOW, the associated Serial Driver is disabled and internally
powered down. If both Serial Drivers for a channel are in this
disabled state, the associated internal logic for that channel is
also powered down. When OELE returns LOW, the values
present on the BOE[7:0] inputs are latched in the Output
Enable Latch, and remain there until OELE returns HIGH to
enable the latch. A device reset (TRSTZ sampled LOW) clears
this latch and disables all Serial Drivers.
NOTE: When all transmit channels are disabled (i.e., both
outputs disabled in all channels) and a channel is re-en-
abled, the data on the Serial Drivers may not meet all timing
specifications for up to 200
µs.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLK input, and
multiples that clock by 10 or 20 (as selected by TXRATE) to
generate a bit-rate clock for use by the Transmit Shifter. It also
provides a character-rate clock used by the transmit paths.
This clock multiplier PLL can accept a REFCLK input between
20 MHz and 150 MHz, however, this clock range is limited by
the operating mode of the CYP15G0401TB clock multiplier
(controlled by TXRATE) and by the level on the SPDSEL input.
When TXRATE = HIGH (Half-rate REFCLK), TXCKSEL =
HIGH or MID (TXCLKx or TXCLKA selected to clock input
register) is an invalid mode of operation.
SPDSEL is a static three-level select [3] (ternary) input that
selects one of three operating ranges for the serial data
outputs and inputs. The operating serial signaling-rate and
allowable range of REFCLK frequencies are listed in Table 9.
The REFCLK
± input is a differential input with each input inter-
nally biased to 1.4V. If the REFCLK+ input is connected to a
TTL, LVTTL, or LVCMOS clock source, REFCLK– can be left
floating and the input signal is recognized when it passes
through the internally biased reference point.
Table 7. TX Modes 5 and 8 Encoding
Characters Generated
X
0
0
Encoded data character
X
0
1
K28.5 fill character
X
1
0
Special character code
X
1
1
16-character Word Sync Sequence
Table 8. Output Enable and BIST Enable Signal Map
BOE
Input
Output
Controlled
(OELE)
BIST
Channel
Enable
(BISTLE)
BOE[7]
OUTD2
±
Transmit D
BOE[6]
OUTD1
±
X
BOE[5]
OUTC2
±
Transmit C
BOE[4]
OUTC1
±
X
BOE[3]
OUTB2
±
Transmit B
BOE[2]
OUTB1
±
X
BOE[1]
OUTA2
±
Transmit A
BOE[0]
OUTA1
±
X
Table 9. Operating Speed Settings
SPDSEL
TXRATE
REFCLK
Frequency
(MHz)
Signaling
Rate (MBaud)
LOW
1
reserved
195–400
0
19.5–40
MID (Open)
1
20–40
400–800
0
40–80
HIGH
1
40–75
800–1500
0
80–150
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