PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 9 of 30
CYP15G0401TB HOTLink II Operation
The CYP15G0401TB is a highly configurable device designed
to support reliable transfer of large quantities of data, using
high-speed serial links, from one source to one or multiple
destinations. This device supports four single-byte or
single-character channels.
CYP15G0401TB Transmit Data Path
Operating Modes
The transmit path of the CYP15G0401TB supports four
character-wide data paths. These data paths are used in
multiple operating modes as controlled by the TXMODE[1:0]
inputs.
Input Register
The bits in the Input Register for each channel support
different assignments, based on if the character is unencoded,
encoded with two control bits, or encoded with three control
bits. These assignments are shown in Table 1. Each Input
Register captures a minimum of eight data bits and two control
bits on each input clock cycle. When the Encoder is bypassed,
the TXCTx[1:0] control bits, are part of the preencoded 10-bit
character.
When the Encoder is enabled (TXMODE[1]
≠ LOW), the
TXCTx[1:0] bits are interpreted along with the associated
TXDx[7:0] character to generate the specific 10-bit trans-
mission character. When TXMODE[0]
≠ HIGH, an additional
special character select (SCSEL) input is also captured and
interpreted. This SCSEL input is used to modify the encoding
of the associated characters. When the transmit Input
Registers are clocked by a common clock (TXCLKA
↑ or
REFCLK
↑), this SCSEL input can be changed on a
clock-by-clock basis and affects all four channels.
When operated with a separate input clock on each transmit
channel, this SCSEL input is sampled synchronous to
TXCLKA
↑. While the value on SCSEL still affects all channels,
it is interpreted when the character containing it is read from
the transmit Phase-align Buffer (where all four paths are inter-
nally clocked synchronously).
Phase-align Buffer
Data from the Input Registers are passed either to the Encoder
or to the associated Phase-align Buffer. When the transmit
paths are operated synchronous to REFCLK
↑ (TXCKSEL
= LOW and TXRATE = LOW), the Phase-align Buffers are
bypassed and data is passed directly to the Parity Check and
Encoder blocks to reduce latency.
When an Input-Register clock with an uncontrolled phase
relationship to REFCLK is selected (TXCKSEL
≠ LOW) or if
data is captured on both edges of REFCLK (TXRATE = HIGH),
the Phase-align Buffers are enabled. These buffers are used
BOE[7:0]
LVTTL Input,
asynchronous,
internal pull-up
BIST and Serial Output, and Enables. These inputs are passed to and through the
Output Enable Latch when OELE is HIGH, and captured in this latch when OELE
returns LOW. These inputs are passed to and through the BIST Enable Latch when
BISTLE is HIGH, and captured in this latch when BISTLE returns LOW.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high
for
≥5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset
automatically upon application of power to the device.
TCLK
LVTTL Input,
internal pull-down
JTAG Test Clock
TDO
Three-state
LVTTL Output
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
TDI
LVTTL Input, internal pull-up Test Data In. JTAG data input port.
Power
VCC
+3.3V Power
GND
Signal and power ground for all internal circuits.
Pin Descriptions (continued)
CYP15G0401TB Quad HOTLink II Transmitter
Pin Name
I/O Characteristics
Signal Description
Table 1. Input Register Bit Assignments [4]
Signal Name
Unencoded
Encoded
2-bit
Control
3-bit
Control
TXDx[0] (LSB)
DINx[0]
TXDx[0]
TXDx[0]
TXDx[1]
DINx[1]
TXDx[1]
TXDx[1]
TXDx[2]
DINx[2]
TXDx[2]
TXDx[2]
TXDx[3]
DINx[3]
TXDx[3]
TXDx[3]
TXDx[4]
DINx[4]
TXDx[4]
TXDx[4]
TXDx[5]
DINx[5]
TXDx[5]
TXDx[5]
TXDx[6]
DINx[6]
TXDx[6]
TXDx[6]
TXDx[7]
DINx[7]
TXDx[7]
TXDx[7]
TXCTx[0]
DINx[8]
TXCTx[0]
TXCTx[0]
TXCTx[1] (MSB)
DINx[9]
TXCTx[1]
TXCTx[1]
SCSEL
N/A
N/A
SCSEL
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