ADA4356ABCZ datasheet(40/61 Pages) AD

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Data Sheet

ADA4356

analog.com

Rev. 0

40 of 61

100MHz LPF cutoff frequency provides the higher bandwidth needed for narrow pulse widths that are required for

closely spaced event detection necessary for datacenter applications. Additional noise floor reduction is possible

via real-time averaging.

Clocks

For optimum performance, drive the ADC sample clock inputs, CLKP (F11) and CLKN (E11), with a differential signal.

The clock signal is typically AC-coupled into the CLKP and CLKN balls via a transformer or capacitors. These balls are

biased internally (see Figure 75) and require no external bias.

Clock Input Options

The ADA4356 has a flexible clock input structure. The clock input can be a CMOS, LVDS, low-voltage positive emitter

coupled logic (LVPECL), or sine wave signal. Regardless of the type of signal used, clock source jitter is an important

consideration, as described in the Jitter Considerations section.

Figure 85 and Figure 86 show two preferred methods for clocking the ADA4356 (at clock rates up to 1GHz prior to the

internal clock divider). A low jitter clock source is converted from a single-ended signal to a differential signal using

either an RF transformer or an RF balun.

Figure 85. Transformer-Coupled Differential Clock (up to 200MHz)

Figure 86. Balun-Coupled Differential Clock (up to 1GHz)

The RF balun configuration is recommended for clock frequencies between 125MHz and 1GHz, and the RF

transformer configuration is recommended for clock frequencies from 10MHz to 200MHz.

If a low jitter clock source is not available, another option is to AC-couple(d) a differential PECL signal to the sample

clock input balls, as shown in Figure 87. For a list of PECL drivers with excellent jitter performance that are suitable

for this application, see Table 10.

Figure 87. Differential PECL Sample Clock (up to 1GHz)

0.1µF

CLOCK

INPUT

50Ω

100Ω

CLKN

CLKP

ADC

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR

0.1µF

CLOCK

INPUT

0.1µF

50Ω

CLKN

CLKP

ADC

100Ω

0.1µF

240Ω

50kΩ

CLKN

CLKP

CLOCK

INPUT

CLOCK

INPUT

ADC

PECL DRIVER

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