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STM32L412C8I6TR Datasheet(PDF) 93 Page - STMicroelectronics

No. de pieza STM32L412C8I6TR
Descripción Electrónicos  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 100DMIPS, up to 128KB Flash, 40KB SRAM, analog, ext. SMPS
PDF  192 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L412C8I6TR Datasheet(HTML) 93 Page - STMicroelectronics

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DS12469 Rev 4
93/192
STM32L412xx
Electrical characteristics
163
Table 36. Typical current consumption in Run modes, with different codesrunning from
Flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V)
Symbol
Parameter
Conditions(1)
TYP
Unit
TYP
Unit
-
Voltage
scaling
Code
25 °C
25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz
all peripherals
Reduced code(2)
0.86
mA
33
µA/MHz
Coremark
0.77
29
Dhrystone 2.1
0.78
30
Fibonacci
0.73
28
While(1)
0.68
26
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 37. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1
Symbol
Parameter
Conditions
TYP
Unit
TYP
Unit
-
Voltage
scaling
Code
25 °C
25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals
disable
Reduced code(1)
2.00
mA
77
µA/MHz
Coremark
2.00
77
Dhrystone 2.1
2.05
79
Fibonacci
2.00
77
While(1)
1.85
71
Reduced code(1)
7.15
mA
89
µA/MHz
Coremark
7.00
88
Dhrystone 2.1
7.15
89
Fibonacci
7.10
89
While(1)
6.60
83
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI = 2 MHz
all peripherals disable
Reduced code(1)
180
µA
90
µA/MHz
Coremark
180
90
Dhrystone 2.1
185
93
Fibonacci
170
85
While(1)
170
85
1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.



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