TDA7546 datasheet(33/68 Pages) STMICROELECTRONICS

33 / 68 page

TDA7546

Functional description

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receiving bad signal is shorter than the decreasing time of the flywheel counter,

then the RDS will keep its synchronization and stores RDS data every 22ms.

Section 3:

After leaving the tunnel, the signal is getting better and the RDS will be

synchronized again as described in section 1.

5.2.7

RAM buffer

The RAM buffer can store up to 24 RDS blocks (rds_bd_h[7:0] and rds_bd_l[7:0]) with their

related information (rds_qu[7:0] and rds_corrp[7:0]) (Figure 7):

Figure 8.

RAM buffer usage

After power up, or after resynchronization by setting “ar_res” rds_int[5] to one, incoming

RDS blocks are stored in the RAM buffer when synchronization has been established

(Figure 8.). But if the bit “syncw” rds_bd_ctrl[0] (refer to page 50) is cleared, every received

RDS block is stored, also without synchronization. This means if the RDS is not

synchronized, every received consecutive 26 RDS data bits are treated as a RDS block.

Figure 9.

RAM buffer update depends on “syncw” bit rds_bd_ctrl[0]

rds_qu[7..0]

rds_corrp[7..0]

rds_bd_h[7..0]

rds_bd_l[7..0]

rds_bd_ctrl[7..0]

sinc4reg[7..0]

testreg[7..0]

rds_int[7..0]

INTERNAL REGISTERS

RAM BUFFER

(24 blocks)

I2C/SPI SHIFT REGISTER

SA_DATAOUT

(spi mode)

SDA_DATAIN

(i2c mode)

rds_qu[7..0]

rds_corrp[7..0]

rds_bd_h[7..0]

rds_bd_l[7..0]

rds_bd_ctrl[7..0]

sinc4reg[7..0]

testreg[7..0]

rds_int[7..0]

read access

(internal)

write access

(external)

pllreg4[7..0]

pllreg0[7..0]

pllreg4[7..0]

Block A

Block B

Block C

RDS data

bits

Write to RAM

Buffer if

"syncw" = 1

Write to RAM

Buffer if

"syncw" = 0

Synchro-

nization flag

"synch"

time

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