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LTC2641/LTC2642

26412f

BLOCK DIAGRAMS

16-BIT DATA LATCH

CONTROL

LOGIC

16-/14-/12-BIT DAC

VDD

REF

VOUT

GND

2641 BD

16-BIT SHIFT REGISTER

POWER-ON

RESET

LTC2641-16

LTC2641-14

LTC2641-12

SCLK

DIN

CLR

16-BIT DATA LATCH

CONTROL

LOGIC

16-/14-/12-BIT DAC

INV

RFB

VDD

REF

VOUT

GND

2642 BD

16-BIT SHIFT REGISTER

POWER-ON

RESET

LTC2642-16

LTC2642-14

LTC2642-12

SCLK

DIN

CLR

LTC2641

LTC2642

TIMING DIAGRAM

SCK

SDI

CS/LD

26412 TD

OPERATION

General Description

The LTC2641/LTC2642 family of 16-/14-/12-bit voltage

output DACs offer full 16-bit performance with less than

±2LSB integral linearity error and less than ±1LSB differen-

tial linearity error, guaranteeing monotonic operation. They

operate from a single supply ranging from 2.7V to 5.5V,

consuming 120μA (typical). An external voltage reference

of 2V to VDD determines the DAC’s full-scale output volt-

age. A 3-wire serial interface allows the LTC2641/LTC2642

to ﬁt into a small 8-/10-pin MSOP or DFN 3mm

× 3mm

package.

Digital-to-Analog Architecture

The DAC architecture is a voltage switching mode resis-

tor ladder using precision thin-ﬁlm resistors and CMOS

switches. The LTC2641/LTC2642 DAC resistor ladders are

composed of a proprietary arrangement of matched DAC

sections. The four MSBs are decoded to drive 15 equally

weighted segments, and the remaining lower bits drive

successively lower weighted sections. Major carry glitch

impulse is very low at 500pV•sec, CL = 10pF, ten times

lower than previous DACs of this type.

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