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LTC1867IGN Datasheet(PDF) 4 Page - Linear Technology

No. de pieza LTC1867IGN
Descripción Electrónicos  12-/16-Bit, 8-Channel 200ksps ADCs
PDF  16 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
Logo LINER - Linear Technology

LTC1867IGN Datasheet(HTML) 4 Page - Linear Technology

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LTC1863/LTC1867
4
18637f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Supply Voltage
(Note 9)
4.75
5.25
V
IDD
Supply Current
fSAMPLE = 200ksps
q
1.3
1.8
mA
NAP Mode
150
µA
SLEEP Mode
q
0.2
3
µA
PDISS
Power Dissipation
q
6.5
9
mW
TI I G CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE
Maximum Sampling Frequency
q
200
kHz
tCONV
Conversion Time
q
3
3.5
µs
tACQ
Acquisition Time
q
1.5
1.1
µs
fSCK
SCK Frequency
40
MHz
t1
CS/CONV High Time
Short CS/CONV Pulse Mode
q
40
100
ns
t2
SDO Valid After SCK
CL = 25pF (Note 11)
q
13
22
ns
t3
SDO Valid Hold Time After SCK
CL = 25pF
q
511
ns
t4
SDO Valid After CS/CONV
CL = 25pF
q
10
30
ns
t5
SDI Setup Time Before SCK
q
15
–6
ns
t6
SDI Hold Time After SCK
q
10
4
ns
t7
SLEEP Mode Wake-Up Time
CREFCOMP = 10µF, CVREF = 2.2µF60
ms
t8
Bus Relinquish Time After CS/CONV
CL = 25pF
q
20
40
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND without latchup. These pins are not
clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 200ksps at 25°C, tr = tf = 5ns and
VIN– = 2.5V for bipolar mode unless otherwise specified.
Note 6: Linearity, offset and gain error specifications apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867 and between 0000 0000 0000 and
0000 0000 0001 for LTC1863. Bipolar offset is the offset voltage
measured from –1/2LSB when output code flickers between 0000 0000
0000 0000 and 1111 1111 1111 1111 for LTC1867, and between
0000 0000 0000 and 1111 1111 1111 for LTC1863.
Note 9: Recommended operating conditions. The input range of
±2.048V
for bipolar mode is measured with respect to VIN– = 2.5V.
Note 10: Guaranteed by design, not subject to test.
Note 11: t2 of 25ns maximum allows fSCK up to 20MHz for rising capture
with 50% duty cycle and fSCK up to 40MHz for falling capture (with 3ns
setup time for the receiving logic).
POWER REQUIRE E TS The q denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
LTC1863/LTC1867/LTC1867A



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