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LTC1863/LTC1867

18637f

TI I G DIAGRA S

t5 (SDI Setup Time Before SCK↑),

t6 (SDI Hold Time After SCK↑)

50%

0.4V

t7 (SLEEP Mode Wake-Up Time)

SCK

CS/CONV

t8 (BUS Relinquish Time)

CS/CONV

SDO

2.4V

t4 (SDO Valid After CONV↓)

CS/CONV

SDO

2.4V

0.4V

2.4V

0.4V

SCK

SDI

2.4V

0.4V

2.4V

0.4V

SDO

1867 TD

SLEEP BIT (SLP = 0)

READ-IN

10%

90%

Hi-Z

t1 (For Short Pulse Mode)

t2 (SDO Valid Before SCK↑),

t3 (SDO Valid Hold Time After SCK↓)

CS/CONV

SCK

50%

Overview

The LTC1863/LTC1867 are complete, low power multi-

plexed ADCs. They consist of a 12-/16-bit, 200ksps ca-

pacitive successive approximation A/D converter, a preci-

sion internal reference, a configurable 8-channel analog

input multiplexer (MUX) and a serial port for data transfer.

Conversions are started by a rising edge on the CS/CONV

input. Once a conversion cycle has begun, it cannot be

restarted. Between conversions, the ADCs receive an input

word for channel selection and output the conversion

result, and the analog input is acquired in preparation for

the next conversion. In the acquire phase, a minimum time

of 1.5

µs will provide enough time for the sample-and-hold

capacitors to acquire the analog signal.

During the conversion, the internal differential 16-bit

capacitive DAC output is sequenced by the SAR from the

most significant bit (MSB) to the least significant bit

(LSB). The input is sucessively compared with the binary

weighted charges supplied by the differential capacitive

DAC. Bit decisions are made by a low-power, differential

comparator. At the end of a conversion, the DAC output

balances the analog input. The SAR contents (a 12-/16-bit

data word) that represent the analog input are loaded into

the 12-/16-bit output latches.

APPLICATIO S I FOR ATIO

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