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ELANSC310 Datasheet(PDF) 59 Page - Advanced Micro Devices |
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ELANSC310 Datasheet(HTML) 59 Page - Advanced Micro Devices |
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59 / 119 page ![]() Élan™SC310 Microcontroller Data Sheet 59 PREL IMINARY ALTERNATE PIN FUNCTIONS To provide the system designer with the most flexibility, the ÉlanSC310 microcontroller provides a means for reconfiguring some of the pin functions, depending on the system requirements. Reconfiguration of the ÉlanSC310 microcontroller pin functions is accom- plished in one of two ways, depending on the pin func- tions that are to be reconfigured. To select the CPU local bus interface or maximum ISA bus interface, the state of the DTR and RTS pins are sampled on the ris- ing edge of the RESIN and IORESET signals when power is first applied to the ÉlanSC310 microcontroller. This is shown in Figure 8. After power has been initially applied and RESIN and IORESET are deasserted, additional assertions of IORESET while RESIN = 1 will not cause the pin con- figurations to change. However, the pin configuration inputs are always sampled in response to RESIN as- sertions. Table 26 shows the pin states at reset to en- able the two different pin configurations involving the Local Bus and Maximum ISA Bus. The bus configura- tion selected can be read in bits 5–6 of the Memory Configuration 1 Register, Index 66h, after the reset. . The second method of reconfiguring ÉlanSC310 micro- controller pin functions is accomplished by program- ming the internal configuration registers. This method is used to configure the following functions: n DRAM or SRAM main memory interface n Unidirectional or bidirectional parallel port n Clock source driving the X1OUT[BAUDOUT] pin n 14.336-MHz clock Table 26. Bus Option Select Bit Logic Bus Selected DTR/CFG1 RTS/CFG0 Local Bus 10 Full/Maximum ISA 11 VCC RESIN and IORESET RTS DTR DTR and RTS sampled at the rising edge of RESIN and IORESET Notes: This is shown to illustrate when CFG0 and CFG1 are sampled and is not intended to be used for reset timings. For reset timings, refer to Table 45 on page 88. Figure 8. Bus Option Configuration Select |
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