CS5560

DS713A5

9

7/31/07

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

16. SDO will be high impedance when CS is high. In some systems it may require a pull-down resistor.

Parameter

Symbol

Min

Typ

Max

Unit

Serial Port Timing in SEC Mode (SMODE = VLR)

SCLK(in) Pulse Width (High)

-

30

-

-

ns

SCLK(in) Pulse Width (Low)

-

30

-

-

ns

CS hold time (high) after RDY falling

10

-

-

ns

CS hold time (high) after SCLK rising

10

-

-

ns

CS low to SDO out of Hi-Z

(Note 16)

-10

-

ns

Data hold time after SCLK rising

-10

-

ns

Data setup time before SCLK rising

10

-

-

ns

CS hold time (low) after SCLK rising

10

-

-

ns

RDY rising after SCLK falling

-10

-

ns

MCLK

SCLK(i)

SDO

CS

RDY

LSB

MSB

Figure 3. SEC Mode - Read Timing (Not to Scale)