CS5560

DS713A5

7

7/31/07

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

12. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resister.

13. SCLK = MCLK/2.

Parameter

Symbol

Min

Typ

Max

Unit

Serial Port Timing in SSC Mode (SMODE = VL)

RDY falling to MSB stable

--2

-

MCLKs

Data hold time after SCLK rising

-10

-

ns

Serial Clock (Out)

Pulse Width (low)

(Note 12, 13)

Pulse Width (high)

50

50

-

-

-

-

ns

ns

RDY rising after last SCLK rising

-8

-

MCLKs

MCLK

RDY

SCLK(o)

SDO

MSB

MSB–1

LSB

LSB+1

CS

Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale)