ADBMS2950BCCSZ datasheet(44/97 Pages) AD

44 / 97 page

ADBMS2950B

Data Sheet

Rev. 0 | Page 44 of 97

The gain error of the IxADC is slightly dependent on the

IxADC input signal, which leads to a small amount of

systematic nonlinearity. The TME calculation in Figure 35 is

based on the worst-case gain error values of ±0.1% and a typical

nonlinearity of ±0.06%. The calculated TME is below the

specified maximum TME of 0.2% for signals above 5 mV, at

ACCN = 32.

The VBxADCs run in lockstep with IxADC, and so their

accumulators average the same number of samples as for the

IxADC channels. Figure 36 shows the VBxADC TME as a

function of the input signal.

Compared to the IxADCs, the impact of noise is relatively

small. At larger inputs, the VBxADC may exhibit some

nonlinearity, which is shown in Figure 36 as an increase in

offset.

Figure 36. VBxADC TME vs. Input Voltage

OVERCURRENT MANAGEMENT

The ADBMS2950B provides functions for overcurrent

management. Three overcurrent ADCs (OC1ADC to

OC3ADC) are provided for triple redundancy. Individual

overcurrent comparator thresholds (OC1TH to OC3TH) and a

common deglitch filter setting (OCDGT) are programmable.

The output of the threshold comparators OC1 to OC3 are fed

into deglitch filters, then into latches OC1L to OC3L, and then

into redundant majority voters controlling the output pins OCA

and OCB.

Overcurrent events are signaled through the OCA and OCB

pins either in the PWM mode or in a static style, as selected by

OCMODE. Independent of the mode, the polarity (OCAX,

OCBX) and the output type can be configured to be either

open-drain or push-pull (OCOD). To accommodate both single

and dual shunt applications, a gain of 1× or 2× can be selected

per overcurrent channel (OC1GC to OC3GC).

Individual overcurrent conversion results are provided at the

conversion rate of 16 kHz through registers OC1R to OC3R.

For the 3rd ADC (OC3ADC), the minimum and maximum

conversion results are tracked within registers OC3MAX and

OC3MIN.

OCx Output Pin Behavior

During power-down and after power-up or SRST, the OCA and

OCB pins are in a high impedance state. This allows defining of

the logic level of the OCx pin through pull-up or pull-down

resistors as required for the application. Caution must be taken

when pulling-up the OCx pins to a voltage rail that is powered

independent of the VREG power rail, as the internal clamping

diodes feed the IC supply current from the OCx pins to the

VREG pin. In this scenario, an external Schottky diode from

such a power rail to the VREG rail must be placed.

Once the ADBMS2950B is powered-up, the host controller can

configure the mode and polarity of the OCx pins as required

through the configuration registers OCAX, OCBX, OCMODE,

and OCOD.

The OCx pins enable their output drivers conservatively to

prevent false positives. They are in a high impedance state when

OCEN = 0, regardless of the OCMODE or OCOD settings.

Whenever OCEN transitions from 0 to 1 after OCMODE has

been set to a non-zero value, the OC pins initially remain in a

high impedance state and only activate their output drivers after

an interval of 10 OCxADC conversion cycles (OCDP = 0). This

ensures that the OCx output is always aligned with the

deglitchers, configured through OCDGT, that are reset at the

OCEN transition. The bit OCDP, when set, reduces the interval

to 3 OCxADC conversion cycles. For the static or any of the

PWM modes, the OCDP allows faster reconfiguration as it is

required for Overcurrent Configuration Update, or manual

assertion of the OCx outputs as it is required for the Crash

Signal Management.

The CLRFLAG command asserting any of the bits OC1L,

OC2L, OC3L re-trigger the interval during which OCA and

OCB are high impedance. Similarly, the CLRFLAG command

asserting bits OCAL and/or OCBL re-trigger the interval for

OCA and/or OCB during which the respective pin has high

impedance. In both the cases, the deglitchers reset as well.

Whenever OCEN transitions from 0 to 1 when OCMODE is 0,

the OC pins remain high impedance. The static mode

(OCMODE = 0b11) and any combination of OCAX, OCBX

allows performing connectivity tests of the OCA, OCB pins and

the connected circuitry.

The actual state of the OCA and OCB pins can be readback

directly through the read-only bits OCAP and OCBP in the

STAT registers. However, in either PWM1 or PWM2 mode, the

state of the pins changes too frequently so that the useful

function of these bits is limited to the static mode and to

diagnostics. Therefore, the additional OCAGD and OCBGD

bits in the FLAG register are used to indicate if the state of the

respective pins differs from the intention of output control,

irrespective of whether the OC outputs are configured in static

or in any PWM mode.

ADBMS2950BCCSZ Datasheet(PDF) 44 Page - Analog Devices

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