ADAU1761BCPZ-R7 datasheet(61/92 Pages) AD

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Data Sheet

ADAU1761

CONTROL REGISTERS

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Rev. F | 61 of 92

Table 65. Serial Port Control 0 Register

Bits

Bit Name

Description

SPSRS

Serial port sampling rate source.

0 = converter rate set in Register R17 (default).

1 = DSP rate set in Register R57.

LRMOD

LRCLK mode sets the LRCLK for either a 50% duty cycle or a pulse. The pulse mode should be at least 1 BCLK wide.

0 = 50% duty cycle (default).

1 = pulse mode.

BPOL

BCLK polarity sets the BCLK edge that triggers a change in audio data. This can be set for the falling or rising edge of the BCLK.

0 = falling edge (default).

1 = rising edge.

LRPOL

LRCLK polarity sets the LRCLK edge that triggers the beginning of the left channel audio frame. This can be set for the falling or rising edge

of the LRCLK.

0 = falling edge (default).

1 = rising edge.

[2:1]

CHPF[1:0]

Channels per frame sets the number of channels per LRCLK frame.

Setting

Channels per LRCLK Frame

Stereo (default)

TDM 4

TDM 8

Reserved

Serial data port bus mode. Both LRCLK and BCLK are main of the serial port when set in main mode and are serial port subordinate in

subordinate mode.

0 = subordinate mode (default).

1 = main mode.

R16: Serial Port Control 1, 16,406 (0x4016)

Table 66.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BPF[2:0]

ADTDM

DATDM

MSBP

LRDEL[1:0]

Table 67. Serial Port Control 1 Register

Bits

Bit Name

Description

[7:5]

BPF[2:0]

Number of bit clock cycles per LRCLK audio frame.

Setting

Bit Clock Cycles

000

64 (default)

001

Reserved

010

011

128

100

256

101

Reserved

110

Reserved

111

Reserved

ADTDM

ADC serial audio data channel position in TDM mode.

0 = left first (default).

1 = right first.

DATDM

DAC serial audio data channel position in TDM mode.

0 = left first (default).

1 = right first.

MSBP

MSB position in the LRCLK frame.

ADAU1761BCPZ-R7 Datasheet(PDF) 61 Page - Analog Devices

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