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SCF5249VM140 Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc |
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SCF5249VM140 Datasheet(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 56 page  Electrical Characteristics SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 37 Figure 9. SDRAM Write Cycle Table 23. Debug AC Timing Specification Num Characteristic Units Min Max D1 PSTCLK to signal Valid (Output valid) --- 6 nSec D2 PSTCLK to signal Invalid (Output hold) 1.8 — nSec D31 Signal Valid to PSTCLK (Input setup) 3 — nSec D4 PSTCLK to signal Invalid (Input hold) 5 — nSec 1. DSCLK and DSI are internally synchronized. This setup time must be met only if recognition on a particular clock is required. 2. AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is different, the input and output timing specifications would need to be adjusted to match the clock load. |
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