TDA8002ATSLASH3SLASHC2 datasheet(16/28 Pages) PHILIPS

16 / 28 page

1997 Nov 04

Philips Semiconductors

Product speciﬁcation

IC card interface

TDA8002

Crystal connections (XTAL1 and XTAL2)

Cext

external capacitors

note 1

−

fxtal

resonance frequency

note 2

−

MHz

Data lines

GENERAL

tedge

delay between falling edge of

I/O, AUX1, AUX2 and I/OUC,

AUX1UC, AUX2UC

−

200

−

delay between falling edge of

I/OUC, AUX1UC, AUX2UC and

I/O, AUX1, AUX2

−

200

−

tr, tf

rise and fall times

Ci =Co =30pF

−−

0.5

µs

DATA LINES I/O, AUX1 AND AUX2

VOH(I/O)

HIGH-level output voltage on

data lines

IOH = −20 µAVCC − 0.5 −

VCC + 0.1 V

IOH = −100 µA

3.5

−−

VOL(I/O)

LOW-level output voltage on

data lines

II/O =1mA

−−

300

VIH(I/O)

HIGH-level input voltage on data

lines

1.8

−

VCC

VIL(I/O)

LOW-level input voltage on data

lines

−

0.8

VI/O(idle)

voltage on data lines outside a

session

−−

0.4

Rpu

internal pull-up resistance

between data lines and VCC

810

Ω

Iedge

current from data lines when

active pull-up is active

−

IIL(I/O)

LOW-level input current on data

lines

VIL = 0.4 V

−−−600

µA

IIH(I/O)

HIGH-level input current on data

lines

VIH =VCC

−−

µA

DATA LINES I/OUC, AUX1UC AND AUX2UC

VOH(I/OUC)

HIGH-level output voltage on

data lines

IOH = −20 µAVDD − 1

−

VDD + 0.2 V

VOL(I/OUC)

LOW-level output voltage on

data lines

II/OUC =1mA

−−

300

VIH(I/OUC)

HIGH-level input voltage on data

lines

0.7VDD

−

VDD

VIL(I/OUC)

LOW-level input voltage on data

lines

−

0.3VDD

ZI/OUC(idle)

impedance on data lines outside

a session

−−

Ω

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

TDA8002AT/3/C2 Datasheet(PDF) 16 Page - NXP Semiconductors

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