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MPC8555CPXAPF Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

No. de pieza MPC8555CPXAPF
Descripción Electrónicos  PowerQUICC??III Integrated Communications Processor Hardware Specifications
PDF  88 Pages
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8555CPXAPF Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc

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MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
46
Freescale Semiconductor
CPM
Figure 26 shows the SCC/SMC/SPI 1,2external clock.
Figure 26. SCC/SMC/SPI AC Timing External Clock Diagram
Figure 27 shows the SCC/SMC/SPI 1,2 internal clock.
Figure 27. SCC/SMC/SPI AC Timing Internal Clock Diagram
Figure 28 shows TDM input and output signals.
Figure 28. TDM Signal AC Timing Diagram
1 SPI AC timings are internal mode when it is master since SPICLK is an
output, and external mode when it is slave.
2 SPI AC timings refer always to SPICLK.
Serial CLKIN
tNEIXKH
tNEIVKH
tNEKHOX
Input Signals:
(See Note)
Output Signals:
(See Note)
Note:
SCC/SMC/SPI
SCC/SMC/SPI
The clock edge is selectable on SCC and SPI.
BRG_OUT
tNIIXKH
tNIKHOX
Input Signals:
(See Note)
Output Signals:
(See Note)
Note:
tNIIVKH
SCC/SMC/SPI
SCC/SMC/SPI
The clock edge is selectable on SCC and SPI.
Serial CLKIN
tTDKHOX
TDM Input Signals
There are 4 possible TDM timing conditions:
tTDIVKH
tTDIXKH
TDM Output Signals
Note:
1.
2.
3.
4.
Input sampled on the rising edge and output driven on the rising edge (shown).
Input sampled on the rising edge and output driven on the falling edge.
Input sampled on the falling edge and output driven on the falling edge.
Input sampled on the falling edge and output driven on the rising edge.



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