Analog Integrated Circuit Device Data

8

Freescale Semiconductor

33887

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS (9)

, (10), (11), (12)

Junction-to-Board (Bottom Exposed Pad Soldered to Board)

HSOP (6.0 W)

PQFN (4.0 W)

SOICW-EP (2.0 W)

~7.0

~8.0

~9.0

°C/W

Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (13)

HSOP (6.0 W)

PQFN (4.0 W)

SOICW-EP (2.0 W)

~41

~50

~62

°C/W

Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p)

(14)

HSOP (6.0 W)

PQFN (4.0 W)

SOICW-EP (2.0 W)

~18

~21

~23

°C/W

Junction-to-Case (Exposed Pad) (15)

HSOP (6.0 W)

PQFN (4.0 W)

SOICW-EP (2.0 W)

~0.8

~1.2

~2.0

°C/W

Notes

9

The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.

10

values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die

less than 5.0 °C/W for maximum load at 70°C ambient. Module thermal design must be planned accordingly.

11

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board near the package.

12

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

13

Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.

14

Per JEDEC JESD51-6 with the board horizontal.

15

Indicates the maximum thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

MAXIMUM RATINGS (continued)

All voltages are with respect to ground unless otherwise noted.

Rating

Symbol

Value

Unit