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MC68HC908GR4MP Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc |
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MC68HC908GR4MP Datasheet(HTML) 74 Page - Freescale Semiconductor, Inc |
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74 / 286 page  Clock Generator Module (CGMC) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 74 Freescale Semiconductor When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES, and R = 1. If fRCLK cannot meet this requirement, use the following equation to solve for R with practical choices of fRCLK, and choose the fRCLK that gives the lowest R. 4. Select a VCO frequency multiplier, N. Reduce N/R to the lowest possible R. 5. If N is < Nmax, use P = 0. If N > Nmax, choose P using this table: Then recalculate N: 6. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS. 7. Select the VCO’s power-of-two range multiplier E, according to this table: 8. Select a VCO linear range multiplier, L, where fNOM = 38.4 kHz Current N Value P 0 1 2 3 Frequency Range E 0 < fVCLK < 8 MHz 0 9,830,400 ≤ f VCLK < 16 MHz 1 19,660,800 ≤ f VCLK < 32 MHz 2 NOTE: Do not program E to a value of 3. R round R MAX f VCLKDES f RCLK -------------------------- ⎝⎠ ⎜⎟ ⎛⎞ integer f VCLKDES f RCLK -------------------------- ⎝⎠ ⎜⎟ ⎛⎞ – ⎩⎭ ⎨⎬ ⎧⎫ × = N round Rf VCLKDES × f RCLK ------------------------------------- ⎝⎠ ⎜⎟ ⎛⎞ = 0N <N max ≤ N max N <N max 2 × ≤ N max 2 × N <N max 4 × ≤ N max 4 × N <N max 8 × ≤ N round Rf VCLKDES × f RCLK 2 P × ------------------------------------- ⎝⎠ ⎜⎟ ⎛⎞ = f VCLK 2 P NR ⁄ × () f RCLK × = f BUS f VCLK () 4 ⁄ = L round f VCLK 2 E f NOM × -------------------------- ⎝⎠ ⎜⎟ ⎛⎞ = |
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