MC68HC908GR4MP datasheet(60/286 Pages) FREESCALE

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Analog-to-Digital Converter (ADC)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

5.7.2 ADC Data Register

One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC

conversion completes.

5.7.3 ADC Clock Register

The ADC clock register (ADCLK) selects the clock frequency for the ADC.

ADIV2–ADIV0 — ADC Clock Prescaler Bits

ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal

ADC clock. Table 5-2 shows the available clock configurations. The ADC clock should be set to

approximately 1 MHz.

Address:

$0003D

Bit 7

654321

Bit 0

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Write:

Reset:

00000000

= Unimplemented

Figure 5-3. ADC Data Register (ADR)

Address:

$0003E

Bit 7

654321

Bit 0

Read:

ADIV2

ADIV1

ADIV0

ADICLK

0000

Write:

Reset:

00000000

= Unimplemented

Figure 5-4. ADC Clock Register (ADCLK)

Table 5-2. ADC Clock Divide Ratio

ADIV2

ADIV1

ADIV0

ADC Clock Rate

ADC input clock

÷ 1

ADC input clock

÷ 2

ADC input clock

÷ 4

ADC input clock

÷ 8

ADC input clock

÷ 16

X = don’t care

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