M29F800DB datasheet(14/53 Pages) STMICROELECTRONICS

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Bus operations

M29F800DT

14/53

Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus

Write, Output Disable, Standby and Automatic Standby. See Table 2: Bus operations, BYTE

= VIL, and Table 3: Bus operations, BYTE = VIH for a summary. Typically glitches of less

than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus

operations.

3.0.1

Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command

Interface. A valid Bus Read operation involves setting the desired address on the Address

Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write

Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 10: Read Mode

AC waveforms, and Table 12: Read AC characteristics for details of when the output

becomes valid.

3.0.2

Bus Write

Bus Write operations write to the Command Interface. A valid Bus Write operation begins by

setting the desired address on the Address Inputs. The Address Inputs are latched by the

Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs

last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of

Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,

during the whole Bus Write operation. See Figure 11: Write AC waveforms, Write Enable

controlled, Figure 12: Write AC waveforms, Chip Enable controlled, Table 13: Write AC

characteristics, Write Enable controlled, and Table 14: Write AC characteristics, Chip

Enable controlled, for details of the timing requirements.

3.0.3

Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

3.0.4

Standby

When Chip Enable is High, VIH, the memory enters Standby mode and the Data

Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to

the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the

Standby current level see Table 11: DC characteristics.

During program or erase operations the memory will continue to use the Program/Erase

Supply Current, ICC3, for Program or Erase operations until the operation completes.

3.0.5

Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or

more the memory enters Automatic Standby where the internal Supply Current is reduced to

the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

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