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AT80C51RB2-3CSIM Datasheet(PDF) 74 Page - ATMEL Corporation |
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AT80C51RB2-3CSIM Datasheet(HTML) 74 Page - ATMEL Corporation |
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74 / 83 page  75 AT80C51RD2/AT83C51Rx2 4113B–8051–03/05 External Data Memory Read Cycle Serial Port Timing - Shift Register Mode Table 54. Symbol Description Table 55. AC Parameters for a Fix Clock Table 56. AC Parameters for a Variable Clock ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 T AVWL T LLWL T RLAZ ADDRESS A8-A15 OR SFR P2 T RHDZ T WHLH T RLRH T LLDV T RHDX T LLAX T AVDV Symbol Parameter T XLXL Serial port clock cycle time T QVHX Output data set-up to clock rising edge T XHQX Output data hold after clock rising edge T XHDX Input data hold after clock rising edge T XHDV Clock rising edge to input data valid Symbol -M -L Units Min Max Min Max T XLXL 300 300 ns T QVHX 200 200 ns T XHQX 30 30 ns T XHDX 00 ns T XHDV 117 117 ns Symbol Type Standard Clock X2 Clock X Parameter for - M Range X Parameter for -L Range Units T XLXL Min 12 T 6 T ns T QVHX Min 10 T - x 5 T - x 50 50 ns T XHQX Min 2 T - x T - x 20 20 ns T XHDX Min x x 0 0 ns T XHDV Max 10 T - x 5 T- x 133 133 ns |
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