FXPS7115D4S datasheet(41/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

There are 4 DSP Configuration registers which are DSP_CFG_U1, DSP_CFG_U3, DSP_CFG_U4, and

DSP_CFG_U5.

7.7.11.1 Self-test control bits

The self-test control bits of the DSP user configuration register (DSP_CFG_U5, address 44h) select one of the

various analog and digital self-test features of the device as shown in Table 73. The self-test control bits are not

included in the read/write array error detection.

7.7.11.2 DSP_CFG_U1 - DSP user configuration #1 register (address 40h)

The DSP user configuration register #1 is a user programmable read/write register that contains DSP-specific

configuration information. This register is included in the read/write array error detection.

Changes to this register reset the DSP data path. The contents of the SNSDATA_x registers are not guaranteed

until the DSP has completed initialization as specified in Table 105. Reads of the SNSDATA_x registers and

sensor data requests should be prevented during this time.

Bit

Symbol

LPF[3:0]

reserved

Factory default

Access

R/W

Table 64. DSP_CFG_U1 - DSP user configuration #1 register (address 40h) bit allocation

LPF[3]

LPF[2]

LPF[1]

LPF[0]

Low Pass Filter Type

800 Hz, 4-Pole

1000 Hz, 4-Pole[1][2]

Table 65. Low-pass filter selection bits (LPF[3:0])

[1]

Default is 1000 Hz.

[2]

In case of POR, filter reverts to the default.

Note: Using values other than those listed in Table 65 causes an error in the DEVSTAT.

7.7.11.3 DSP_CFG_U3 - DSP user configuration #3 register (address 42h)

The DSP user configuration register #3 is a user programmable read/write register that contains DSP-specific

configuration information. This register is included in the read/write array error detection.

Changes to this register reset the DSP data path. The content of the SNSDATA_x registers are not guaranteed

until the DSP has completed initialization. Reads of the SNSDATA_x registers and sensor data requests should

be prevented during this time.

This register is readable and writeable in SPI mode, and I2C mode.

Bit

Symbol

reserved

DATATYPE0[1:0]

reserved

DATATYPE1[1:0]

reserved

Reset

Access

R/W

Table 66. DSP_CFG_U3 - DSP user configuration #3 register (address 42h) bit allocation

FXPS7115D4S

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Objective data sheet

Rev. 1.2 — 28 June 2023

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