FXPS7115D4S datasheet(33/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

Bit[1][2] Symbol

Description

0 — No error detected

1 — Error detected in the continuity of the edge seal monitor circuit

Table 40. DEVSTAT1 - device status register (address 02h) bit description...continued

[1]

During POR and soft reset ignore DEVSTAT1 error flags, refer to Section 7.5.5.

[2]

A common timer is used for all error bits in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV. This bit is cleared based

on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 7.7.4.

7.7.2.3 DEVSTAT2 - device status register (address 03h)

Bit

Symbol

F_OTP_

ERR

U_OTP_

ERR

U_RW_ERR

U_W_

ACTIVE

reserved

TEMP0_

ERR

reserved

Reset

reserved

Access

Table 41. DEVSTAT2 - device status register (address 03h) bit allocation

Bit

Symbol

Description

F_OTP_ERR

The NXP factory OTP array error bit is set if a fault is detected in the factory OTP array.

This error is cleared by a read of the DEVSTAT2 register through any communication

interface or on a data transmission that includes the error in the status field.

0 — No error detected

1 — Error detected in the NXP factory OTP array

U_OTP_ERR

The user OTP array error bit is set if a fault is detected in the user OTP array. This error is

cleared by a read of the DEVSTAT2 register through any communication interface or on a

data transmission that includes the error in the status field.

0 — No error detected

1 — Error detected in the user OTP array

U_RW_ERR

When ENDINIT is set, an error detection is enabled for all user writable registers. The

error detection code is continuously calculated on the user writable registers and verified

against a previously calculated error detection code. If a mismatch is detected in the error

detection, the U_RW_ERR bit is set. This error is cleared by a read of the DEVSTAT2

error in the status field.

0 — No error detected

1 — Error detected in the user read/write array

U_W_ACTIVE

The user OTP write in process status bit is set if a user initiated write to OTP is in process.

The U_W_ACTIVE bit is automatically cleared once the write to OTP is complete.

0 — No OTP write in process

1 — OTP write in process

TEMP0_ERR

The temperature error bit is set if an overtemperature or undertemperature condition

exists. This error is cleared by a read of the DEVSTAT2 register through any

communication interface or on a data transmission that includes the error in the status

field.

0 — No error detected

1 — Overtemperature or undertemperature error condition detected

Table 42. DEVSTAT2 - device status register (address 03h) bit description

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1.2 — 28 June 2023

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