ICSSSTUAF32869A

14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

2

ICSSSTUAF32869A

7095/14

Parity Implementation and Device Wiring

Block Diagram

NOTE:

1.This range does not include D1, D4, and D7, and their corresponding outputs.

Register 1

(Front)

Register 2

(Back)

PARIN

PARIN, W4

NC, A8

PPO, W8

NC, A4

PTYERR, W1

NC, A11

PPO, W4

NC, A8

Set C=0 for Register 1, and C=1 for Register 2

PPO

RESET

CLK

CLK

DODT

QODTA

QODTB

QCKEA

QCKEB

R

D

Q

R

D

Q

DCKE

PTYERR

R

D

Q

Q14A

Q14B

Q1A

Q1B

R

D

Q

R

D

Q

VREF

PARITY GENERATOR

AND CHECKER

QCSA

QCSB

R

D

Q

PARIN

D1

D14

DCS0

11

2

2

2

CSR

(CS Active)

2

2

(1)

(1)

(1)