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HC705RC17GRS/D Datasheet(PDF) 73 Page - NXP Semiconductors |
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HC705RC17GRS/D Datasheet(HTML) 73 Page - NXP Semiconductors |
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73 / 126 page  Carrier Modulator Transmitter (CMT) Modulator MC68HC705RC17 — Rev. 2.0 General Release Specification Carrier Modulator Transmitter (CMT) Figure 9-4. Modulator Block Diagram 9.5.1 Time Mode When the modulator operates in time mode, the modulation mark and space periods consist of zero or an integer number of fosc ÷ 8 clocks (= 250 kHz @ 2 MHz osc). This provides a modulator resolution of 4 µs and a maximum mark and space periods of about 16 ms (each). However, to prevent carrier glitches which could affect carrier spectral purity, the modulator control gate and carrier clock are synchronized. The carrier signal is activated when the modulator gate opens. The modulator gate can only close when the carrier signal is low. (The output logic level during space periods is low). If the carrier generator is in baseband mode (BASE bit in MCSR is high), the modulator output will be at a logic 1 for the duration of the mark period and at a logic 0 for the duration of a space period. See Figure 9-5. =? 0 fOSC EOC FLAG MBUFF SBUFF SREG * 13-BIT DOWN COUNTER * * DENOTES HIDDEN REGISTER 12 BITS 12 BITS 12 12 CONTROL/STATUS REGISTER MODULATOR EOC INTERRUPT ENABLE BASE MODE ÷ 8 CLOCK CONTROL CARRIER OUT LOAD MBUFF/SBUFF SYSTEM CONTROL MODULATOR GATE OUT PRIMARY/SECONDARY SELECT . . MODULATOR MODULATOR/ CARRIER GENERATOR ENABLE DIV2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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