HC705RC17GRSSLASHD datasheet(39/126 Pages) NXP

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Interrupts

Reset Interrupt Sequence

MC68HC705RC17 — Rev. 2.0

General Release Specification

Interrupts

The M68HC05 CPU does not support interruptible instructions. The

maximum latency to the first instruction of the interrupt service routine

must include the longest instruction execution time plus stacking

overhead.

Latency = (Longest instruction execution time + 10) x tcyc seconds

An return from interrupt (RTI) instruction is used to signify when the

interrupt software service routine is completed. The RTI instruction

causes the register contents to be recovered from the stack and normal

processing to resume at the next instruction that was to be executed

when the interrupt took place. Figure 4-1 shows the sequence of events

that occurs during interrupt processing.

4.4 Reset Interrupt Sequence

The reset function is not in the strictest sense an interrupt; however, it is

acted upon in a similar manner as shown in Figure 4-1. A low-level input

on the RESET pin or an internally generated RST signal causes the

program to vector to its starting address, which is specified by the

contents of memory locations $3FFE and $3FFF. The I bit in the

condition code register is also set. The MCU is configured to a known

state during this type of reset.

4.5 Software Interrupt (SWI)

The SWI is an executable instruction and a nonmaskable interrupt since

it is executed regardless of the state of the I bit in the CCR. If the I bit is

zero (interrupts enabled), the SWI instruction executes after interrupts

that were pending before the SWI was fetched or before interrupts

generated after the SWI was fetched. The interrupt service routine

address is specified by the contents of memory locations $3FFC and

$3FFD.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705RC17GRS/D Datasheet(PDF) 39 Page - NXP Semiconductors