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HC705JB2GRS/H Datasheet(PDF) 88 Page - NXP Semiconductors

No. de pieza HC705JB2GRS/H
Descripción Electrónicos  Industry standard M68HC05 CPU core
PDF  128 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
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HC705JB2GRS/H Datasheet(HTML) 88 Page - NXP Semiconductors

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GENERAL RELEASE SPECIFICATION
August 28, 1998
UNIVERSAL SERIAL BUS MODULE
MC68HC705JB2
10-20
REV 1.1
1 =
Receive on Endpoint 0 has occurred
0 =
Receive on Endpoint 0 has not occurred
RSTF — USB Reset Flag
This read only bit is set when a valid reset signal state is detected on the D+
and D- lines. This reset detection will also generate an internal reset signal to
reset the CPU and other peripherals including the USB module. This bit is
cleared by writing a logic 1 to the RSTFR bit in the UCR2 register. This bit is
cleared by a POR reset.
SUSPND — USB Suspend Flag
To save power, this read/write bit should be set by the software if a 3ms
constant idle state is detected on USB bus. Setting this bit stops the clock to
the USB and causes the USB module to enter Suspend mode. Unnecessary
analog circuitry will be powered down. Software must clear this bit after the
Resume flag (RESUMF) is set while this Resume interrupt flag is serviced.
TXD0IE — Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt
when the TXD0F bit becomes set.
1 =
USB interrupts enabled for Transmit Endpoint 0
0 =
USB interrupts disabled for Transmit Endpoint 0
RXD0IE — Endpoint 0 Receive Interrupt Enable
This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt
when the RXD0F bit becomes set.
1 =
USB interrupts enabled for Receive Endpoint 0
0 =
USB interrupts disabled for Receive Endpoint 0
TXD0FR — Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.Writing a
logic 0 to TXD0FR has no effect. Reset clears this bit.
RXD0FR — Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.Writing a
logic 0 to RXD0FR has no effect. Reset clears this bit.
10.5.3 USB Interrupt Register 1 (UIR1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UIR1
R
TXD1F
EOPF
RESUMF
0
TXD1IE
EOPIE
00
$003A
W
RESUMFR
TXD1FR
EOPFR
reset
⇒
00000000
= Unimplemented
Figure 10-22. USB Interrupt Register 1(UIR1)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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