AD6472

–7–

REV. 0

Table VI. 40% to 60% Duty Cycle RXCLK Clock

when the RXCLK = 1160 kHz

Symbol

Parameter

Min

Typ

Max

Units

Clock Period

862

ns

Clock Pulsewidth High

342

514

ns

Clock Pulsewidth Low

514

342

ns

Output Delay

8

13

19

ns

Latency

Pipeline Delay

3

3

3

Cycles

Table VII. 40% to 60% Duty Cycle RXCLK when the

RXCLK = 1160

2 kHz

Symbol

Parameter

Min

Typ

Max

Units

Clock Period

431

ns

Clock Pulsewidth High

171

257

ns

Clock Pulsewidth Low

257

171

ns

Output Delay

8

13

19

ns

Latency

Pipeline Delay

3

3

3

Cycles

Receive Interface Timing

The analog input is sampled at the rising edge of the RXCLK.

The digital data, RX11:RX0, is valid on each falling edge of

RXCLK. Figure 4 shows a three-cycle latency on the receive

data.

Table V through Table VII lists the RXCLK clock switching

specifications for various RXCLK conditions. See Table IV,

Configuration Control.

Table V. 40% to 60% Duty Cycle when the RXCLK

= 1168

÷ 2 kHz

Symbol

Parameter

Min

Typ

Max

Units

Clock Period

1712

ns

Clock Pulsewidth High

685

1027

ns

Clock Pulsewidth Low

1027

685

ns

Output Delay

8

13

19

ns

Latency

Pipeline Delay

3

3

3

Cycles

DATA1

S4

S3

S2

S1

ANALOG

INPUT

INPUT

CLOCK

RXCLK

OUTPUT

DATA

RX11:RX0

Figure 4. Receive Interface Timing Diagram

10ns

2

TX_CLK

TX_SYNC

TX_DATA

D11

MSB

D10

D9

D8

D7

D5

D6

D4

D3

D2

D1

D0

X

X

X

X

D11

MSB

D10

D9

1. THE RISING EDGE TO TX_SYNC CAN OCCUR ANYWHERE. TX_SYNC MUST BE AT LEAST ONE CLOCK CYCLE WIDE.

2. TX_SYNC FALLING EDGE MUST OCCUR AFTER THE TX_CLK RISING EDGE THAT CAPTURED THE SERIAL LSB.

THIS ENSURES CORRECT LOADING INTO THE DAC.

FULL SCALE

1/2 FULL SCALE

1/2 FULL SCALE

OUTPUT

MINUS 1LSB

ZERO

011111111111

000000000000

111111111111

WORD

100000000000

1

THE FIRST 12 BITS OF THE 16-BIT SERIAL WORD ARE THE INPUT TO THE TX PATH DAC, MSB FIRST. THE NUMBER

SYSTEM IS TWOS COMPLEMENT, AS FOLLOWS:

12ns

Figure 5. Transmit Interface Timing Diagram