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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AD6472 Datasheet(PDF) 4 Page - Analog Devices |
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AD6472 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 8 page  AD6472 –4– REV. 0 Pin Mnemonic Description 1 +5 V_DVDD +5 V Digital Supply. 2 DGND Digital Ground. 3 MODE_SEL0 Bit Rate—Filter Corner Select. 4 MODE_SEL1 Bit Rate—Filter Corner Select. 5 AA_FLTR_BP Antialiasing Filter Bypass. 6 PWRDN Power-Down Active Low. 7 NC No Connect. 8 TX_GAIN_SEL Transmit Attenuation (6 dB) Select. 9 TX_DRVR_BP Transmit Driver Bypass. 10 ADC_BUF_BP ADC Buffer Bypass. 11 TX_LPF_BP Transmit Filter Bypass. 12 TSTGND Factory test pin. Connect to DGND. 13 LOOPBACK Loopback Select. 14 DGND Digital Ground. 15 +3 V_DVDD +3.3 V Digital Supply. 16 TX_DATA Transmit Data Input. 17 TX_SYNC Transmit Data Frame Sync Input. 18 TX_CLK Transmit Clock Input. 19 +5 V_DVDD +5 V Digital Supply. 20 DGND Digital Ground. 21 NC No Connect. 22 IOUT_SET DAC Output Current Full Scale (With Resistor to Ground). 23 NC No Connect. 24 CAP_B Decoupling Pin for Internal Node. 25 CAP_C Decoupling Pin for Internal Node. 26 TX_IOUT_A TXDAC Complementary Current Output. 27 TX_IOUT_B TXDAC Complementary Current Output. 28 AGND Analog Ground. 29 AVDD +5 V Analog Supply. 30 TX_LPF_IN_B Differential Input to LPF. 31 TX_LPF_IN_A Differential Input to LPF. 32 TX_LPF_OUT_B Differential Output from Transmit (If Driver Bypassed). 33 TX_LPF_OUT_A Differential Output from Transmit (If Driver Bypassed). 34 AVDD +5 V Analog Supply. 35 DRVR_OUT_B Differential Driver Output. 36 DRVR_OUT_A Differential Driver Output. 37 AGND Analog Ground. 38 HYB_IN2_B Hybrid Noninverting Input. 39 HYB_IN2_A Hybrid Noninverting Input. 40 HYB_IN1_B Hybrid Inverting Input. PIN CONFIGURATIONS Pin Mnemonic Description 41 HYB_IN1_A Hybrid Inverting Input. 42 AGND Analog Ground. 43 AVDD +5 V Analog Supply. 44 PGA_GC2 PGA Gain Select Bits. 45 PGA_GC1 PGA Gain Select Bits. 46 PGA_GC0 PGA Gain Select Bits. 47 AA_FLTR_OUTB Differential Output of the Antialiasing Filter. 48 AA_FLTR_OUTA Differential Output of the Antialiasing Filter. 49 ADC_INB Differential Input to the ADC. 50 ADC_INA Differential Input to the ADC. 51 REF_COM Reference Common. 52 CAP_TOP Decoupling Pin for ADC Reference. 53 CAP_BOT Decoupling Pin for ADC Reference. 54 VREF External Voltage Reference. 55 CM_LVL Common-Mode Level. (1/2 Supply Voltage, Nominally.) 56 AGND Analog Ground. 57 AVDD +5 V Analog Supply. 58 DGND Digital Ground. 59 +5 V_ DVDD +5 V Digital Supply. 60 NC No Connect. 61 +3 V_ DVDD +3 V Digital Supply. 62 TR_DAC_OUT Timing Recovery DAC Output Voltage. 63 SDATA Serial Data Input to Timing Recov- ery DAC. 64 SFRAME Frame Sync for Timing Recovery. 65 SCLK Clock for Timing Recovery DAC. Serial Data. 66 RX0 Digital Output Data. 67 RX1 Digital Output Data. 68 RX2 Digital Output Data. 69 RX3 Digital Output Data. 70 RX4 Digital Output Data. 71 RX5 Digital Output Data. 72 DGND Digital Ground. 73 +3 V_DVDD +3 V Digital Supply. 74 RX6 Digital Output Data. 75 RX7 Digital Output Data. 76 RX8 Digital Output Data. 77 RX9 Digital Output Data. 78 RX10 Digital Output Data. 79 RX11 Digital Output Data. 80 RXCLK Clock Input for ADC Data. |
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