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AX88780 Datasheet(PDF) 40 Page - ASIX Electronics Corporation |
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AX88780 Datasheet(HTML) 40 Page - ASIX Electronics Corporation |
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40 / 49 page ![]() AX88780 6.2 A.C. Timing Characteristics 6.2.1 Host Clock A. Host site reference clock Description Min Typ. Max Units Reference frequency - 100 - MHz Reference clock duty cycle 40 50 60 % B. PHY site reference clock Description Min Typ. Max Units Reference frequency 25 - 0005% 25 25 + 0.005% MHz Reference clock duty cycle 40 50 60 % 6.2.2 Reset Timing HC L K RS T _ N Tr s t Symbol Description Min Typ. Max Units Trst Reset pulse width 2 - - ms 6.2.3 Host Single Write Timing HCLK CSN WEN Valid address HA[15:1] Valid data HD[31:0] Tsetup Tar Tad Tvalid_cycle Symbol Description Min Typ. Max Units Tsetup CSN,WEN to HCLK setup timing 6 - - ns Tar HA exceed to WEN timing 0 HCLK Tad HA exceed to WEN timing 0 HCLK Tvalid_cycle A Valid write cycle timing 3 - - HCLK 40 ASIX ELECTRONICS CORPORATION |
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