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STPM32TR Datasheet(PDF) 34 Page - STMicroelectronics |
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STPM32TR Datasheet(HTML) 34 Page - STMicroelectronics |
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34 / 121 page  Theory of operation STPM32, STPM33, STPM34 34/121 DS10272 Rev 8 Figure 24. Analog front end internal scheme PLNA uses the chopping technique to cancel the intrinsic offset of the amplifier. A dedicated block generates chopper frequencies for voltage and current channels. The amplified signals are fed to the 2nd order sigma-delta modulator. The analog-to-digital conversion in the STPM3x is carried out using four 2nd order sigma- delta converters. A pseudo-random block generates pseudo-random signals for voltage and current channels. These random signals implement the dithering technique in order to de- correlate the output of the modulators and avoid accumulation points on the frequency spectrum. The device performs A/D conversions of analog signals on four independent channels in parallel. Figure 25. Block diagram of the modulator IIPx IINx VIPx VINx 2 order ΣΔ modulator PLNA GAINx [1:0] DFE bsV bsC 2 order ΣΔ modulator nd nd GIPG1303141321LM ∫ ∫ D/A a1 a2 1st integrator 2nd integrator comparator input Dithering - - stream out GIPG1303141326LM |
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