ST7LUS5 datasheet(70/124 Pages) STMICROELECTRONICS

70 / 124 page

On-chip peripherals

ST7LUS5, ST7LU05, ST7LU09

70/124

Figure 33.

PWM signal example

Output compare mode

To use this function, the OE bit must be 0, otherwise the compare is done with the shadow

and DCR0L registers. This value will be loaded immediately (without waiting for an OVF

event).

The DCR0H must be written first, the output compare function starts only when the DCR0L

value is written.

When the 12-bit up counter (CNTR) reaches the value stored in the DCR0H and DCR0L

registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is

generated if the CMPIE bit is set.

Note:

The output compare function is only available for DCRx values other than 0 (reset value).

Caution:

At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value

has not yet been written (in this case, the shadow register will contain the new DCR0H value

and the old DCR0L value), then:

- If OE = 1 (PWM mode): the compare is done between the timer counter and the shadow

- if OE = 0 (OCMP mode): the compare is done between the timer counter and DCRx. There

is no PWM signal.

The compare between DCRx or the shadow register and the timer counter is locked until

DCR0L is written.

10.2.4

Low power modes

COUNTER

FFDh

FFEh

FFFh

FFDh

FFEh

FFFh

FFDh

FFEh

DCR0 = FFEh

ATR = FFDh

fCOUNTER

Table 38.

Effect of low power modes on AT timer

Mode

Description

Slow

The input frequency is divided by 32

Wait

No effect on AT timer

Active Halt

AT timer halted except if CK0 = 1, CK1 = 0 and OVFIE = 1

Halt

AT timer halted

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