TC35680FSG datasheet(21/91 Pages) TOSHIBA

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TC35680FSG-002/TC35681FSG-002

2019-04-04

Hardware Start-up Sequence

The sequence of the start-up of the power supply and the reset deassertion are shown in Figure 3-3. For sequence of the start-up of

the built-in firmware, refer to Section 3.5. For details of the reset, refer to Section 4.5.

The VBAT power should be supplied first. The VDDIO power can be supplied simultaneously. The voltage of the VDDIO, however,

should not exceed the voltage of the VBAT. The reset should be deasserted after the voltage of the VBAT reaches the minimum

value of VBATopr in Section 5.2 and the voltage of the VDDIO also reaches the minimum value of VDDIOopr.

When the reset is deasserted, the crystal oscillator for the reference clock starts to operate.

And the SiOSC starts oscillating to supply the sleep clock.

The reference clock should become stable in 1.5 ms for a circuit of TC35680/TC35681. It is needed that a stable time of the reference

clock keeps within1.5 ms

Figure 3-3 Hardware start-up sequence

VDDIO power supply

Reset signal

→Reset deassertion is necessary after VDDIO becomes stable.

Reference clock

Oscillation

VBAT power supply

Operation start

Sleep clock

(SiOSC)

Oscillation

Never be VBAT < VDDIO.

Built-in LDO regulator and

DC/DC converter

↑

LDO regulator ON

DC/DC

Converter ON

→

After the sleep clock is detected, PMU switches it.

(Temporal transition to the Sleep mode)

Boot completion

Minimum value of VBATopr at start-up (Section 5.2)

Boot start

Oscillation

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