L9396 datasheet(68/109 Pages) STMICROELECTRONICS

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System functional safety implementations

L9396

68/109

DS12539 Rev 6

7.2.3

Reset output

RESET output pin conveys the active low reset signal generated by the device in case of

over / under voltage conditions on the µC supply rails or when a watchdog error (either from

WD1 or WD2) is asserted.

It is implemented as an open drain output, therefore an external source can be connected to

this output. An external 5 kΩ typ pull-up is recommended to ensure the proper functionality.

RESET output is able to operate and force output low also in standby mode only if VBST

supply is present.

Figure 11. Reset input logic diagram

Three internal reset signals are generated by the device:



POR: Power On Reset - This reset is asserted when GNDD is open or a failure is

detected in the internal supplies or bandgap circuits. When active, all other resets are

asserted.



WSM_RESET: Watchdog State Machine Reset - This reset is generated when the POR

is active or when a failure is detected in the VCCx or VCORE supply.



SSM_RESET: System State Machine Reset - This reset is asserted when the POR or

the WSM_RESET are active, or when a failure is detected in either Watchdog state

machine.

The RESET pin is the active-low signal driven on the output pin, and is an inverted form of

SSM_RESET.

The cause of a RESET activation is latched and reported into the SUPPLY CONTROL

REGISTERS and cleared upon SPI reading.

The reset logic shall be controlled as shown in the diagram below:

GADG2401171129PS

GNDSUBx

GNDA

VCCx

VCORE pin

VINTD

VINTA

(Reference)

VBGR

(Monitor)

VBGM

Monitor

GNDA

Monitor

VCCx

Monitor

VCORE

Monitor

VINTD

Monitor

VINTA

VCCx_UV

VCCx_OV

VCORE_UV

VCORE_OV

VINTD_UV

VINTD_OV

VINTA_UV

VINTA_OV

Controlling all supplies

Reference for

VBG_READY

GNDA_ERR

VCCx_ERR

VCORE_ERR

VREG_ERR

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