UPSD3313D-40T6T datasheet(33/231 Pages) STMICROELECTRONICS

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uPSD33xx

Table 7. Logical Instruction Set

Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.

Mnemonic(1)

and Use

Description

Length/Cycles

ANL

A, Rn

AND register to ACC

1 byte/1 cycle

ANL

A, direct

AND direct byte to ACC

2 byte/1 cycle

ANL

A, @Ri

AND indirect SRAM to ACC

1 byte/1 cycle

ANL

A, #data

AND immediate data to ACC

2 byte/1 cycle

ANL

direct, A

AND ACC to direct byte

2 byte/1 cycle

ANL

direct, #data

AND immediate data to direct byte

3 byte/2 cycle

ORL

A, Rn

OR register to ACC

1 byte/1 cycle

ORL

A, direct

OR direct byte to ACC

2 byte/1 cycle

ORL

A, @Ri

OR indirect SRAM to ACC

1 byte/1 cycle

ORL

A, #data

OR immediate data to ACC

2 byte/1 cycle

ORL

direct, A

OR ACC to direct byte

2 byte/1 cycle

ORL

direct, #data

OR immediate data to direct byte

3 byte/2 cycle

SWAP

Swap nibbles within the ACC

1 byte/1 cycle

XRL

A, Rn

Exclusive-OR register to ACC

1 byte/1 cycle

XRL

A, direct

Exclusive-OR direct byte to ACC

2 byte/1 cycle

XRL

A, @Ri

Exclusive-OR indirect SRAM to ACC

1 byte/1 cycle

XRL

A, #data

Exclusive-OR immediate data to ACC

2 byte/1 cycle

XRL

direct, A

Exclusive-OR ACC to direct byte

2 byte/1 cycle

XRL

direct, #data

Exclusive-OR immediate data to direct byte

3 byte/2 cycle

CLR

Clear ACC

1 byte/1 cycle

CPL

Compliment ACC

1 byte/1 cycle

Rotate ACC left

1 byte/1 cycle

RLC

Rotate ACC left through the carry

1 byte/1 cycle

Rotate ACC right

1 byte/1 cycle

RRC

Rotate ACC right through the carry

1 byte/1 cycle

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