PPC5604BAMLL6R datasheet(35/109 Pages) NXP

35 / 109 page

Package pinouts and signal descriptions

MPC5604B/C Microcontroller Data Sheet, Rev. 15

NXP Semiconductors

Table 13. Recommended operating conditions (5.0 V)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

VSS

SR Digital ground on VSS_HV pins

—

VDD

SR Voltage on VDD_HV pins with respect to

ground (VSS)

—4.5

5.5

Voltage drop2

3.0

5.5

VSS_LV

SR Voltage on VSS_LV (low voltage digital

supply) pins with respect to ground (VSS)

—VSS−0.1

VSS+0.1

VDD_BV

SR Voltage on VDD_BV pin (regulator supply)

with respect to ground (VSS)

—4.5

5.5

Voltage drop2

3.0

5.5

Relative to VDD

VDD−0.1 VDD+0.1

VSS_ADC

SR Voltage on VSS_HV_ADC (ADC reference)

pin with respect to ground (VSS

—VSS−0.1

VSS+0.1

VDD_ADC

SR Voltage on VDD_HV_ADC pin (ADC

reference) with respect to ground (VSS)

—4.5

5.5

Voltage drop2

3.0

5.5

Relative to VDD

VDD−0.1 VDD+0.1

VIN

SR Voltage on any GPIO pin with respect to

ground (VSS)

—VSS−0.1

—

Relative to VDD

—VDD+0.1

IINJPAD

SR Injected input current on any pin during

overload condition

—

−55

IINJSUM

SR Absolute sum of all injected input currents

during overload condition

—

−50

TVDD

SR VDD slope to ensure correct power up

—3.07

0.25 V/µs

V/s

TA C-Grade Part

SR Ambient temperature under bias

fCPU

≤ 64 MHz

−40

°C

TJ C-Grade Part

SR Junction temperature under bias

−40

110

TA V-Grade Part

SR Ambient temperature under bias

−40

105

TJ V-Grade Part

SR Junction temperature under bias

−40

130

TA M-Grade Part

SR Ambient temperature under bias

−40

125

TJ M-Grade Part

SR Junction temperature under bias

−40

150

1 100 nF capacitance needs to be provided between each V

DD/VSS pair.

2 Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain

analog electrical characteristics will not be guaranteed to stay within the stated limits.

3 330 nF capacitance needs to be provided between each V

DD_LV/VSS_LV supply pair.

4 100 nF capacitance needs to be provided between V

DD_BV and the nearest VSS_LV (higher value may be needed

depending on external regulator characteristics).

5 1 µF (electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between V

DD_ADC/VSS_ADC pair.

Another ceramic cap of 10 nF with low inductance package can be added.

6 Guaranteed by device validation.

7 Minimum value of TV

DD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).

PPC5604BAMLL6R Datasheet(PDF) 35 Page - NXP Semiconductors

PPC5604BAMLL6R Datasheet(HTML) 35 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL