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UCD7100 Datasheet(PDF) 9 Page - Texas Instruments |
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UCD7100 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 30 page ![]() 5 10 15 20 25 30 35 40 45 5 7.5 10 12.5 15 VDD − Supply Voltage − V CLOAD = 10 nF CLOAD = 4.7 nF CLOAD = 2.2 nF CLOAD = 1 nF Figure 8-8. Fall Time vs Supply Voltage 0 5 10 15 20 5 7.5 10 12.5 15 VDD − Supply Voltage − V CLOAD = 10 nF CLOAD = 4.7 nF CLOAD = 2.2 nF CLOAD = 1 nF Figure 8-9. Propagation Delay Rising vs Supply Voltage 5 10 15 20 25 5 7.5 10 12.5 15 VDD − Supply Voltage − V CLOAD = 10 nF CLOAD = 4.7 nF CLOAD = 2.2 nF CLOAD = 1 nF Figure 8-10. Propagation Delay Falling vs Supply Voltage −50 50 125 −25 0 25 75 100 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 TJ − Temperature − °C Figure 8-11. Default Current Limit Threshold vs Temperature −50 50 125 −25 0 25 75 100 0 5 10 15 20 25 30 35 40 TJ − Temperature − °C Figure 8-12. CS to OUTx Propagation Delay vs Temperature −50 50 −25 0 25 75 100 0 5 10 15 20 25 30 35 40 45 50 TJ − Temperature − °C 125 Figure 8-13. CS to CLF Propagation Delay vs Temperature www.ti.com UCD7100 SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCD7100 |
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