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SH7041A Datasheet(PDF) 360 Page - Renesas Technology Corp

No. de pieza SH7041A
Descripción Electrónicos  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
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SH7041A Datasheet(HTML) 360 Page - Renesas Technology Corp

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12.2.16
Timer Period Buffer Register (TCBR)
The timer period buffer register (TCBR) is a 16-bit register used only in complementary PWM
mode. It functions as a buffer register for the TCDR register. The TCBR register values are
transferred to the TCDR register with the transfer timing established in the TMDR register. The
TCBR register is initialized to H'FFFF by a power-on reset or in standby mode. Manual reset does
not initialize TCBR. Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit
units.
Bit:
15
14
13
12
11
10
9
8
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
12.3
Bus Master Interface
12.3.1
16-Bit Registers
The timer counters (TCNT) and general registers (TGR) are 16-bit registers. A 16-bit data bus to
the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit
units. Figure 12.3 shows an example of 16-bit register access operation.
TCNTH
TCNTL
Bus
interface
Upper 8 bits
Lower 8 bits
Bus master
Internal data bus
Module data bus
Figure 12.3 16-Bit Register Access Operation (Bus Master
↔ TCNT (16 Bit))



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