P5021 datasheet(98/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

2.18.1

I2C DC electrical characteristics

This table provides the DC electrical characteristics for the I2C interfaces.

2.18.2

I2C AC electrical specifications

This table provides the AC timing parameters for the I2C interfaces.

Table 56. I2C DC electrical characteristics (OVDD = 3.3 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

VIH

2.0

—

Input low voltage

VIL

—0.8

Output low voltage (OVDD = min, IOL = 2 mA)

VOL

00.4

Pulse width of spikes which must be suppressed by the input

filter

tI2KHKL

050

Input current each I/O pin (input voltage is between

0.1

× OV

DD and 0.9 × OVDD(max)

–40

μA4

Capacitance for each I/O pin

010

—

Notes:

1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.

2. Output voltage (open drain or open collector) condition = 3 mA sink current.

3. See the applicable chip reference manual for information about the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.

Table 57. I2C AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit

Notes

SCL clock frequency

fI2C

0400

kHz

Low period of the SCL clock

tI2CL

1.3

—

μs—

High period of the SCL clock

tI2CH

0.6

—

μs—

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs—

Hold time (repeated) START condition (after this period,

the first clock pulse is generated)

tI2SXKL

0.6

—

μs—

Data setup time

tI2DVKH

100

—

Data input hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

μs3

Data output delay time

tI2OVKL

—0.9

μs4

Setup time for STOP condition

tI2PVKH

0.6

—

μs—

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs—

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